rev. 0.1 7/06 copyright ? 2006 by silicon laboratories AN303 AN303 si55 x vcxo t emperature s tability d efinition 1. introduction the si55x vcxo utilizes a unique architecture to prov ide vcxo functionality and pe rformance in an industry standard 5x7 mm clcc package. this unique architecture provides nearly any clock frequency from 10 mhz to 1.4 ghz and voltage control for closed-lo op applications (phase-locked loops). the basis for frequency synthesis is a single-frequency bulk-acoustic wave (baw) at-cut crystal resonator that offers tight frequency stability over temperature and well unders tood aging behavior. a cmos ic based on silicon labs? proprietary dspll? technology provides the frequ ency translation from the crystal to the desired output frequency. voltage control is achieved via a ground-referenced anal og-to-digital converter (vcadc) that dynamically adjusts the frequency synthesis. 2. temperature effects both traditional vcxos and si55x vcxos have specifications that are dependent on temperature. temperature affects two areas of vcxos: the crystal?s absolute frequen cy across temperature and the control voltage circuitry?s response to temperature. 2.1. crystal temperature behavior baw at-cut crystals have absolute frequency that is dependent on the cut angle and the temperature as shown in figure 1. saw oscillators have a different beha vior. the si55x vcxo data sheet spec ifies this paramete r as ?temperature stability? indicating the base oscillator? s frequency stability across temperature. t he specification is given as a symmetric minimum and maximum. figure 1. relative frequency across temperature for at-cut bulk-acoustic-wave crystal r m r r r r r m y z at-cut bt-cut 49 o 35? o -1 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? -1 ? 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? y- bar quartz z 25 20 15 10 5 0 -5 -10 -15 -20 -25 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 f/f) ppm temperature ( o c)
AN303 2 rev. 0.1 2.2. control voltage temperature behavior the control voltage of the si55x is converted by the vcad c and applied to the internal synthesizer in real-time. the si55x does not pull the crystal to achieve frequency tuning , so, in this way, differs from traditional vcxos. the key advantage of this digital approach is to provide customer orderable tuning slopes (kv). lower kv?s can be advantageous when designing a pll, but this topic is bey ond the scope of this application note. (see an255 for additional detail). the vcadc relies on an internal voltage reference to defi ne the full-scale voltage (conversion range). the internal voltage reference changes with temperature caus ing the kv to vary at a rate of ~0.1%/c (e.g., 0.045 ppm/v per c for kv = 45 ppm/v). the vcadc is ground referenced and therefore provides no frequency adjustment for v c = 0.0 v. the full-scale reference is also reset after each powerup. the reset attempts to calibrate the kv back to its nominal value. together, the variation and reset bound the allowed kv range. the range of kv is specified in the data sheet as a minimum and maximum percent change from the nominal value. the resulting frequency for a given v c voltage for various start-up and operating temperature conditions is shown in figure 2. figure 2. vcxo transfer gain temperature dependency 2.3. measuring the crystal ?s temperature stability because of the secondary effe ct of kv variation, measur ement of the crystal temper ature stability must be made under a specific condition. be cause the vcadc is ground refe renced, applying 0.0 v to the v c input effectively disables the output frequency tuning. once inactive, the vcadc temperature dependency (and kv variation) is removed, and the crystal?s temp erature stability can be observed. vcxo transfer gain temperature dependency for kv = 135ppm/v (nominal) (assumes zero crystal temperature dependency) -200 -150 -100 -50 0 50 100 150 200 250 300 350 400 00.511.522.533.5 control voltage (v) ppm vc range that the pll will hold to maintain to see this curve: start at hot then run at cold to see this curve: start at cold then run at hot nominal vc = family of transfer curves showing the dependency on startup temperature and running temperature worst case ?nominal? vc due to reduced slope @ calibration accuracy
AN303 rev. 0.1 3 3. absolute pull range correct understanding the temperature dependencies of the si55x vcxo allow calcul ation of the absolute pull range (apr). an266 describes this ca lculation in full detail when taking the total pull-range from the minimum guaranteed kv; the minimum apr is calculated by taking the minimum pull-range (minimum v c range times the minimum kv) and subtracting the crystal?s temperature stability and aging stability. 4. conclusion silicon labs? si55x vcxos have two temperature dependencies that are specified ind ependently wit hin the data sheets. the first depende ncy is due to the crystal behavior and is specified as temperatur e stability. the second dependency is due to the v c analog-to-digital converter and is specified as kv range. measurement of the crystal behavior can only be observed if the vcadc is made inactive (i.e., v c = 0.0 v). the resulting apr can be calculated by taking the minimum kv and subtracting the crystal?s temperat ure stability and the crystal?s aging stability.
AN303 4 rev. 0.1 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, texas 78735 tel:1+ (512) 416-8500 fax:1+ (512) 416-9669 toll free:1+ (877) 444-3032 email: vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.
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